View M45PE10_4155562.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M45PE10
1-Mbit, page-erasable serial flash memory with byte-alterability and 75 MHz SPI bus interface
Features

SPI bus compatible serial interface 75 MHz clock rate (maximum) 2.7 V to 3.6 V single supply voltage 1-Mbit of page-erasable Flash memory Page size: 256 bytes - Page write in 11 ms (typical) - Page program in 0.8 ms (typical) - Page erase in 10 ms (typical) Sector erase (512 Kbits) Hardware write protection of the bottom sector (64 Kbytes) Electronic signature - JEDEC standard two-byte signature (4011h) - Unique ID code (UID) with 16 bytes readonly, available upon customer request only in the T9HX process Deep power-down mode 1 A (typical) More than 100 000 write cycles More than 20 years data retention Packages - ECOPACK(R) (RoHS compliant)
VFQPN8 (MP) (MLP8) SO8N (MN) 150 mil width

April 2008
Rev 7
1/47
www.numonyx.com 1
Contents
M45PE10
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Active power, standby power and deep power-down modes . . . . . . . . . . 13 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 6.2 6.3 6.4 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/47
M45PE10 6.4.2
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12
Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 23 Page write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Page erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 8 9 10 11 12 13
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
List of tables
M45PE10
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AC characteristics (75 MHz operation, T9HX (0.11 m) process) . . . . . . . . . . . . . . . . . . . 40 SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4/47
M45PE10
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO and VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20 Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 21 Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22 Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Page program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 31 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SO8N - 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 43 MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline. . . . . . . . . . 44
5/47
Description
M45PE10
1
Description
The M45PE10 is a 1-Mbit (128 Kbit x 8 bit) serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle. The memory is organized as 2 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes. The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction.
Important note
This datasheet details the functionality of the M45PE10 devices, based on the previous T7X process or based on the current T9HX process (available since August 2007). Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008. Figure 1. Logic diagram
VCC
D C S W Reset M45PE10
Q
VSS
AI07403
Figure 2.
SO and VDFPN connections
M45PE10 D C Reset S 1 2 3 4 8 7 6 5
AI07404
Q VSS VCC W
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
6/47
M45PE10 Table 1. Signal names
Signal name C D Q S W Reset VCC VSS Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Reset Supply voltage Ground Input Input Output Input Input Input
Description
Direction
7/47
Signal descriptions
M45PE10
2
2.1
Signal descriptions
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of Serial Clock (C). Data on serial data output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and serial data output (Q) is at high impedance. Unless an internal read, program, erase or write cycle is in progress, the device will be in the standby power mode (this is not the deep power-down mode). Driving Chip Select (S) Low selects the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs are high impedance. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the reset mode, provided that no internal operation is currently in progress. Driving Reset (Reset) Low while an internal operation is in progress has no effect on that internal operation (a write cycle, program cycle, or erase cycle).
2.6
Write Protect (W)
This input signal puts the device in the hardware protected mode, when write protect (W) is connected to VSS, causing the first 256 pages of memory to become read-only by protecting them from write, program and erase operations. When write protect (W) is connected to VCC, the first 256 pages of memory behave like the other pages of memory.
8/47
M45PE10
Signal descriptions
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
9/47
SPI modes
M45PE10
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in standby mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI bus master R CS3 CS2 CS1 S W Reset S W Reset S W Reset SPI memory device VCC VSS R SPI memory device CQD VCC VSS R SPI memory device CQD VCC VSS
Figure 3.
AI12836c
1. The Write Protect (W) signal should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the serial data output (Q) line at a time, the other devices are high impedance. The pull-up resistor R (represented in Figure 3) ensures that no device is selected if the bus master leaves the S line in the high impedance state. In applications where the bus master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the Clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low (while the S line is pulled High). This ensures that S and C do not become High at the same time, and so, that the tSHCH requirement is met.
10/47
M45PE10
SPI modes The typical value of R is 100 k, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is short enough, as the S and C lines must reach the correct state (S = High and C = Low) while the SPI bus is in high impedance. Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the bus master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 4.
CPOL CPHA C
SPI modes supported
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
11/47
Operating features
M45PE10
4
4.1
Operating features
Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a page write (PW) or page program (PP) sequence, which consists of four bytes plus data. This is followed by the internal cycle (of duration tPW or tPP). To share this overhead, the page write (PW) or page program (PP) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The page write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The page write (PW) instruction is entered by driving Chip Select (S) Low, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data bytes are written to the data buffer, starting at the address given in the third address byte (A7-A0). When Chip Select (S) is driven High, the write cycle starts. The remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page then automatically put into an erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings, it is recommended to use the page write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (PW) sequences with each containing only a few bytes (see Section 6.7: Page write (PW), Table 14: AC characteristics (50 MHz operation), and Table 15: AC characteristics (75 MHz operation, T9HX (0.11 m) process)).
12/47
M45PE10
Operating features
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to `1'. This might be:

when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (PE) or sector erase (SE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available when the designer knows that the only changes involve resetting bits to 0 that are still set to `1'. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page.
For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Section 6.8: Page program (PP), Table 14: AC characteristics (50 MHz operation), and Table 15: AC characteristics (75 MHz operation, T9HX (0.11 m) process)).
4.4
Polling during a write, program or erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, or tSE). The write in progress (WIP) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.
4.5
Reset
An internal power on reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (Reset) Low during the power-on process, and only driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode. When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write). The device then goes in to the standby power mode. The device consumption drops to ICC1. The deep power-down mode is entered when the specific instruction (the deep power-down (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the release from deep power-down and read electronic signature (RES) instruction) is executed. All other instructions are ignored while the device is in the deep power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.
13/47
Operating features
M45PE10
4.7
Status register
The status register contains two status bits that can be read by the read status register (RDSR) instruction. See Section 6.4: Read status register (RDSR) for a detailed description of the status register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE10 features the following data protection mechanisms:

Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, erase and write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - - Power-up Reset (Reset) driven Low Write disable (WRDI) instruction completion Page write (PW) instruction completion Page program (PP) instruction completion Page erase (PE) instruction completion Sector erase (SE) instruction completion
The hardware protected mode is entered when write protect (W) is driven Low, causing the first 256 pages of memory to become read-only. When write protect (W) is driven High, the first 256 pages of memory behave like the other pages of memory The Reset (Reset) signal can be driven Low to protect the contents of the memory during any critical time, not just during power-up and power-down In addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions while the device is not in active use.

14/47
M45PE10
Memory organization
5
Memory organization
The memory is organized as:

512 pages (256 bytes each) 131,072 bytes (8 bits each) 2 sectors (512 Kbits, 65536 bytes each) programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1)
Each page can be individually:

The device is page or sector erasable (bits are erased from 0 to 1). Table 2. Memory organization
Sector 1 0 10000h 00000h Address range 1FFFFh 0FFFFh
15/47
Memory organization Figure 5.
Reset W S C D Q Control logic High voltage generator
M45PE10 Block diagram
I/O shift register
Address register and counter
256-byte data buffer
Status register
1FFFFh
Ydecoder
10000h First 256 pages can be made read-only
00000h 256 bytes (page size) X decoder
000FFh
AI07405
16/47
M45PE10
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ) or read status register (RDSR) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a page write (PW), page program (PP), page erase (PE), sector erase (SE), write enable (WREN), write disable (WRDI), deep power-down (DP) or release from deep power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a write cycle, program cycle or erase cycle are ignored, and the internal write cycle, program cycle or erase cycle continues unaffected. Table 3.
Instruction WREN WRDI RDID RDSR READ FAST_READ PW PP PE SE DP RDP
Instruction set
Description Write enable Write disable Read identification Read status register Read data bytes Read data bytes at higher speed Page write Page program Page erase Sector erase Deep power-down Release from deep power-down One-byte instruction code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0011 0000 1011 0000 1010 0000 0010 1101 1011 1101 1000 1011 1001 1010 1011 06h 04h 9Fh 05h 03h 0Bh 0Ah 02h DBh D8h B9h ABh Address Dummy bytes bytes 0 0 0 0 3 3 3 3 3 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Data bytes 0 0 1 to 3 1 to 1 to 1 to 1 to 256 1 to 256 0 0 0 0
17/47
Instructions
M45PE10
6.1
Write enable (WREN)
The write enable (WREN) instruction (Figure 6) sets the write enable latch (WEL) bit. The write enable latch (WEL) bit must be set prior to every page write (PW), page program (PP), page erase (PE), and sector erase (SE) instruction. The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 6. Write enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
6.2
Write disable (WRDI)
The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit. The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions:

Power-up Write disable (WRDI) instruction completion Page write (PW) instruction completion Page program (PP) instruction completion Page erase (PE) instruction completion Sector erase (SE) instruction completion Write disable (WRDI) instruction sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 7.
1
2
3
4
5
6
7
18/47
M45PE10
Instructions
6.3
Read identification (RDID)
The read identification (RDID) instruction allows to read the device identification data:

Manufacturer identification (1 byte) Device identification (2 bytes) A unique ID code (UID) (17 bytes, of which 16 available upon customer request)(a).
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (11h). The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes of the optional customized factory data (CFD) content. The CFD bytes are read-only and can be programmed with customers data upon their demand. If the customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero (00h). Any read identification (RDID) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on serial data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the standby power mode. Once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 4. Read identification (RDID) data-out sequence
Device Identification Memory type 40h Memory capacity 11h CFD length 10h UID(1) CFD content 16 bytes
Manufacturer Identification 20h
1. The unique ID code is available only in the T9HX process (see Important note on page 6).
a. The 17 bytes of unique ID code are available only in the T9HX process (see Important note on page 6).
19/47
Instructions Figure 8.
S 0 C Instruction D Manufacturer identification High Impedance Q MSB 15 14 13 MSB 3 2 1 0 MSB Device identification UID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
M45PE10
Read identification (RDID) instruction sequence and data-out sequence
AI06809c
1. The unique ID code is available only in the T9HX process (see Important note on page 6).
6.4
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the status register continuously, as shown in Figure 9. The status bits of the status register are as follows:
6.4.1
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write, program or erase cycle. When set to `1', such a cycle is in progress, when reset to `0' no such cycle is in progress.
6.4.2
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to `1' the internal write enable latch is set, when set to `0' the internal write enable latch is reset and no write, program or erase instruction is accepted. Table 5.
b7 0 0 0 0 0 0 WEL
(1)
Status register format
b0 WIP(1)
1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device).
20/47
M45PE10 Figure 9.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions Read status register (RDSR) instruction sequence and data-out sequence
0
7
AI02031E
6.5
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip select (S) can be driven High at any time during data output. Any read data bytes (READ) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
21/47
Instructions
M45PE10
Figure 10. Read data bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data out 1 7 6 5 4 3 2 1 0 7 Data out 2
MSB
AI03748D
1. Address bits A23 to A17 are don't care.
22/47
M45PE10
Instructions
6.6
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip select (S) can be driven High at any time during data output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence and data-out sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
1. Address bits A23 to A17 are don't care.
23/47
Instructions
M45PE10
6.7
Page write (PW)
The page write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page write (PW) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (D). The rest of the page remains unchanged if no power failure occurs during this write cycle. The page write (PW) instruction performs a page erase cycle even if only one byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary wrap round, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. If less than 256 data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the page write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (PW) sequences with each containing only a few bytes (see Table AC characteristics (50 MHz operation) and Table 15: AC characteristics (75 MHz operation, T9HX (0.11 m) process)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page write cycle (whose duration is tPW) is initiated. While the page write cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. A page write (PW) instruction applied to a page that is hardware protected is not executed. Any page write (PW) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
24/47
M45PE10 Figure 12. Page write (PW) instruction sequence
S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04045
1. Address bits A23 to A17 are don't care. 2. 1 n 256.
25/47
Instructions
M45PE10
6.8
Page program (PP)
The page program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on serial data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary wrap round, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Table 14: AC characteristics (50 MHz operation) and Table 15: AC characteristics (75 MHz operation, T9HX (0.11 m) process)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the page program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose duration is tPP) is initiated. While the page program cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. A page program (PP) instruction applied to a page that is hardware protected is not executed. Any page program (PP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
26/47
M45PE10 Figure 13. Page program (PP) instruction sequence
S 0 C Instruction 24-bit address Data byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 Data byte 3 Data byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04044
1. Address bits A23 to A17 are don't care. 2. 1 n 256.
27/47
Instructions
M45PE10
6.9
Page erase (PE)
The page erase (PE) instruction sets to `1' (FFh) all bits inside the chosen page. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on serial data input (D). Any address inside the page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed page erase cycle (whose duration is tPE) is initiated. While the page erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. A page erase (PE) instruction applied to a page that is hardware protected is not executed. Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Page erase (PE) instruction sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI04046
1. Address bits A23 to A17 are don't care.
28/47
M45PE10
Instructions
6.10
Sector erase (SE)
The sector erase (SE) instruction sets to `1' (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL). The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on serial data input (D). Any address inside the sector (see Table 2) is a valid address for the sector erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed sector erase cycle (whose duration is tSE) is initiated. While the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. A sector erase (SE) instruction applied to a sector that contains a page that is Hardware Protected is not executed. Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 15. Sector erase (SE) instruction sequence
S 0 C Instruction 24-bit address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
1. Address bits A23 to A17 are don't care.
29/47
Instructions
M45PE10
6.11
Deep power-down (DP)
Executing the deep power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the standby power mode (if there is no internal cycle currently in progress). But this mode is not the deep power-down mode. The deep power-down mode can only be entered by executing the deep power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 11). Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. This releases the device from this mode. The deep power-down mode automatically stops at power-down, and the device always powers-up in the standby power mode. The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the deep power-down mode is entered. Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Deep power-down (DP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Standby mode
Deep power-down mode
AI03753D
30/47
M45PE10
Instructions
6.12
Release from deep power-down (RDP)
Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. Executing this instruction takes the device out of the deep power-down mode. The release from deep power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. The release from deep power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby Power mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any release from deep power-down (RDP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Release from deep power-down (RDP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRDP
High Impedance Q Deep power-down mode Standby mode
AI06807
31/47
Power-up and power-down
M45PE10
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at power-up, and then for a further delay of tVSL VSS at power-down
A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power up, a power on reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the power on reset (POR) threshold value, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP), page erase (PE) and sector erase (SE) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No write, program or erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after wrap round VCC passed the VCC(min) level
These values are specified in Table 6. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for read instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal can be driven Low for the whole duration of the power-up and power-down phases. At power-up, the device is in the following state:

The device is in the standby power mode (not the deep power-down mode) The write enable latch (WEL) bit is reset The write in progress (WIP) bit is reset
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the power on reset (POR) threshold value, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result).
32/47
M45PE10 Figure 18. Power-up timing
VCC VCC(max)
Power-up and power-down
Program, erase and write commands are rejected by the device Chip selection not allowed VCC(min) Reset state of the device VWI tPUW tVSL Read access allowed Device fully accessible
time
AI04009C
Table 6.
Symbol tVSL
(1)
Power-up timing and VWI threshold
Parameter VCC(min) to S low Time delay before the first write, program or erase instruction Write inhibit voltage Min. 30 1 1.5 10 2.5 Max. Unit s ms V
tPUW(1) VWI(1)
1. These parameters are characterized only, over the temperature range -40 C to +85 C.
33/47
Initial delivery state
M45PE10
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to `1' (each byte contains FFh). All usable status register bits are 0.
9
Maximum ratings
Stressing the device outside the ratings listed in Table 7: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7.
Symbol TSTG TLEAD VIO VCC VESD Storage temperature Lead temperature during soldering Input and output voltage (with respect to ground) Supply voltage Electrostatic discharge voltage (human body model)
(2)
Absolute maximum ratings
Parameter Min. -65 Max. 150 Unit C C V V V
See note (1) -0.6 -0.6 -2000 VCC + 0.6 4.0 2000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ).
34/47
M45PE10
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature
Operating conditions
Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
Table 9.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input pulse voltages Input and output timing reference voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC measurement I/O waveform
Input levels 0.8VCC Input and output timing reference levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 10.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min. 8 6 Max. pF pF Unit
1. Sampled only, not 100% tested, at TA=25 C and a frequency of 33 MHz.
35/47
DC and AC parameters Table 11.
Symbol ILI ILO ICC1
M45PE10 DC characteristics
Parameter Test condition (in addition to those in Table 8) Min. Max. 2 2 S = VCC, VIN = VSS or VCC 50 Unit A A A
Input leakage current Output leakage current Standby current (standby and reset modes) Deep power-down current
ICC2
S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 33 MHz, Q = open C = 0.1VCC / 0.9.VCC at 75 MHz, Q = open S = VCC S = VCC - 0.5 0.7VCC IOL = 1.6 mA IOH = -100 A VCC-0.2
10 4
A
ICC3
Operating current (FAST_READ)
mA 12 15 15 0.3VCC VCC+0.4 0.4 mA mA V V V V
ICC4 ICC5 VIL VIH VOL VOH
Operating current (PW) Operating current (SE) Input low voltage Input high voltage Output low voltage Output high voltage
36/47
M45PE10 Table 12. AC characteristics (25 MHz operation)
DC and AC parameters
Test conditions specified in Table 8 and Table 9 Symbol fC fR tCH tCL
(1)
Alt. fC
Parameter Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR Clock frequency for Read instructions
Min. D.C. D.C. 18 18
Typ.
Max. 25 20
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
tCLH tCLL
Clock High time Clock Low time Clock slew rate
(2)
(1)
(peak to peak)
0.03 10 10 5 5 10 10 200 15 15 0 10 3 10 50 100 3 30 11 10.2+ n*0.8/256 1.2 0.4+ n*0.8/256 10 1 5 20 5 25
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tRLRH(2) tRHSL tSHRH tWHSL tSHWL tDP(2) tRDP(2) tPW(3)
tCSS
S active setup time (relative to C) S not active hold time (relative to C)
tDSU tDH
Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C)
tCSH tDIS tV tHO tRST tREC
S deselect time Output disable time Clock Low to Output valid Output hold time Reset pulse width Reset recovery time Chip should have been deselected before Reset is de-asserted Write protect setup time Write protect hold time S to deep power-down S High to standby power mode Page write cycle time (256 bytes) Page write cycle time (n bytes) Page program cycle time (256 bytes)
ns ns ns s s ns ns ns s s ms
tPP(3) tPE tSE
ms ms s
Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time
1. tCH + tCL must be greater than or equal to 1/ fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 3. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 n 256).
37/47
DC and AC parameters Table 13. AC characteristics (33 MHz operation)
33 MHz only available for products marked since week 40 of 2005(1) Test conditions specified in Table 8 and Table 9 Symbol fC fR tCH(2) tCL(2) tCLH tCLL Alt. fC Parameter Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR Clock frequency for READ instructions Clock High time Clock Low time Clock slew rate tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(3) tCLQV tCLQX tTHSL tSHTL tDP(3) tRDP(3) tPW(4) tCSH tDIS tV tHO tDSU tDH tCSS
(3)
M45PE10
Min. D.C. D.C. 13 13
Typ.
Max. 33 20
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
(peak to peak)
0.03 10 10 3 5 5 5 200 12 12 0 50 100 3 30 11 10.2+ n*0.8/256 1.2 0.4+ n*0.8/256 10 1 5 25
S active setup time (relative to C) S not active hold time (relative to C) Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C) S deselect time Output disable time Clock Low to Output valid Output hold time Top Sector Lock setup time Top Sector Lock hold time S to deep power-down S High to standby power mode Page write cycle time (256 bytes) Page write cycle time (n bytes) Page program cycle time (256 bytes)
ns ns ns ns ns s s
ms
tPP(4) tPE tSE
ms
Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time
20 5
ms s
1. Details of how to find the date of marking are given in application note, AN1995. 2. tCH + tCL must be greater than or equal to 1/ fC. 3. Value guaranteed by characterization, not 100% tested in production. 4. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 n 256).
38/47
M45PE10 Table 14. AC characteristics (50 MHz operation)
50 MHz operation for T9HX technology(1) Test conditions specified in Table 8 and Table 9 Symbol fC fR tCH(2) tCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(3) tCLQV tCLQX tWHSL tSHWL tDP(3) tRDP(3) tRLRH(3) tRHSL tSHRH tPW(4) tPP(4) tPE tSE tCSH tDIS tV tHO tDSU tDH tCLH tCLL tCSS Alt. fC Parameter Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR, RDID Clock frequency for read instructions Clock High time Clock Low time Clock slew rate
(3)
DC and AC parameters
Min. D.C. D.C. 9 9
Typ.
Max. 50 33
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
(peak to peak)
0.1 5 5 2 5 5 5 100 8 8 0 50 100 3 30 10 3 10 11 0.8 int(n/8) x 0.025 10 1.5 23 3 20 5
S active setup time (relative to C) S not active hold time (relative to C) Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C) S deselect time Output disable time Clock Low to Output valid Output hold time Write protect setup time Write protect hold time S to deep power-down S High to standby mode
ns ns ns ns ns s s s s ns ms ms ms s
tRST tREC
Reset pulse width Reset recovery time Chip should have been deselected before Reset is de-asserted Page write cycle time (256 bytes) Page program cycle time (256 bytes) Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time
1. Delivery of parts in T9HX process to start from August 2007. 2. tCH + tCL must be greater than or equal to 1/ fC. 3. Value guaranteed by characterization, not 100% tested in production. 4. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2, int(17/8) = 3.
39/47
DC and AC parameters Table 15. AC characteristics (75 MHz operation, T9HX (0.11 m) process(1))(2)
Test conditions specified in Table 8 and Table 9 Symbol fC fR tCH tCL
(3)
M45PE10
Alt. fC
Parameter Clock frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR, RDID Clock frequency for read instructions
Min. D.C. D.C. 6 6
Typ.
Max. 75 33
Unit MHz MHz ns ns V/ns ns ns ns ns ns ns ns
tCLH tCLL tCSS tDSU tDH
Clock High time Clock Low time Clock slew rate(3) (peak to peak)
(3)
0.1 5 5 2 5 5 5 100 8 8 0 20 100 3 30 3 11 0.8 int(n/8) x 0.025(7) 10 1.5 80 4.5 15 23 3 20 5 150 10
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(4)
S active setup time (relative to C) S not active hold time (relative to C) Data in setup time Data in hold time S active hold time (relative to C) S not active setup time (relative to C)
tCSH tDIS tV tHO
S deselect time Output disable time Clock Low to Output valid Output hold time Write protect setup time Write protect hold time S to deep power-down S High to standby mode Write status register cycle time Page write cycle time (256 bytes) Page program cycle time (256 bytes) Page program cycle time (n bytes) Page erase cycle time Sector erase cycle time Subsector erase cycle time Bulk erase cycle time
ns ns ns ns ns s s ms ms ms ms s ms s
tCLQV tCLQX tWHSL(5) tSHWL(5) tDP(3) tRDP(3) tW tPW(6) tPP(6) tPE tSE tSSE tBE
1. See Important note on page 6. 2. Details of how to find the technology process in the marking are given in AN1995, see also Section 12: Ordering information. 3. tCH + tCL must be greater than or equal to 1/ fC. 4. Value guaranteed by characterization, not 100% tested in production. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set to `1'. 6. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 n 256). 7. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
40/47
M45PE10 Figure 20. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 21. Write Protect setup and hold timing
W tWHSL
tSHWL
S
C
D High Impedance Q
AI07439
41/47
DC and AC parameters Figure 22. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
M45PE10
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
Figure 23. Reset AC waveforms
S
tSHRH tRLRH
tRHSL
Reset
AI06808
42/47
M45PE10
Package mechanical
11
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 24. SO8N - 8 lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 16.
SO8N - 8 lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches Max 1.75 0.10 1.25 0.28 0.17 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 0.48 0.23 0.10 5.00 6.20 4.00 - 0.50 8 1.27 0.041 0.193 0.236 0.154 0.050 0.189 0.228 0.150 - 0.010 0 0.016 0.25 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 - 0.020 8 0.050 Typ Min Max 0.069 0.010
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
43/47
Package mechanical
M45PE10
Figure 25. MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline
A R1 D1 B
MCAB bbb
D
aaa C A
E
E1
E2
e
2x
0.10 C B
aaa C B
b
0.10 C A
A2
D2 L
ddd
A
A1 A3
C
70-ME
1. Drawing is not to scale.
Table 17.
MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package mechanical data
millimeters inches Max 1.00 0.05 0.026 0.008 0.35 0.48 0.016 0.236 0.226 3.20 3.60 0.134 0.197 0.187 3.80 - 0.00 0.50 0.75 12 0.15 0.10 0.05 4.30 - 0.157 0.050 0.004 0.024 0.150 - 0.000 0.020 0.029 12 0.006 0.004 0.002 0.169 - 0.126 0.142 0.014 0.019 Typ 0.033 Min 0.031 0.000 Max 0.039 0.002
Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e R1 L aaa bbb ddd 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.10 0.60 0.85 Min 0.80 0.00
44/47
M45PE10
Ordering information
12
Ordering information
Table 18.
Example:
Ordering information scheme
M45PE10 - V MP 6 T G
Device type M45PE = serial flash memory for data storage
Device function 10 = 1-Mbit (128 Kbit x 8)
Operating voltage V = VCC = 2.7 V to 3.6 V
Package MN = SO8 (150 mil width) MP = VDFPN8 6 x 5 mm (MLP8)
Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow
Option blank = standard packing T = tape and reel packing
Plating technology P or G = ECOPACK(R) (RoHS compliant)
For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 m technology, process digit `4'), please contact your nearest Numonyx sales office.
45/47
Revision history
M45PE10
13
Revision history
Table 19.
Date 29-Apr-2003 04-Jun-2003
Document revision history
Version 1.0 1.1 Initial release. Description corrected of entering hardware protected mode (W must be driven, and cannot be left unconnected). VIO(min) extended to -0.6 V, tPW(typ) and tPP(typ) improved. Table of contents, warning about exposed paddle on MLP8, and lead-free options added. Change of naming for VDFPN8 package. Soldering temperature information clarified for RoHS compliant devices. Device grade clarified. Document promoted to preliminary data. Minor wording changes Document promoted to mature datasheet. No other changes Added AC characteristics (33 MHz operation). An easy way to modify data, A fast way to modify data, Page write (PW) and Page program (PP) sections updated to explain optimal use of page write and page program instructions. Updated ICC3 values in Table 11: DC characteristics. Updated Table 18: Ordering information scheme. Added ECOPACK(R) information. Document reformatted. 50 MHz frequency added (Table 14 added). VCC supply voltage and VSS ground descriptions added. Figure 4: SPI modes supported modified and explanatory text added. VIO max modified in Table 7: Absolute maximum ratings. At power-up, The write in progress (WIP) bit is reset tSHQZ end timing line modified in Figure 22: Output timing. Blank option removed below Plating technology in Table 18: Ordering information scheme. Small text changes. Package specifications updated (see Section 11: Package mechanical). Removed `low voltage' from the title. Updated the value for the maximum clock frequency (from 50 to 75 MHz) through the document. Added: Table 15: AC characteristics (75 MHz operation, T9HX (0.11 m) process) and ECOPACK(R) text in Section 11: Package mechanical. Modified: Table 11: DC characteristics, Figure 3: Bus master and memory devices on the SPI bus, and Section 6.3: Read identification (RDID). Minor text changes. Applied Numonyx branding. Changes
04-Dec-2003
1.2
25-Jun-2004 22-Sep-2004 08-Oct-2004
1.3 2.0 3.0
4-Oct-2005
4.0
02-Feb-2007
5
21-Feb-2008
6
01-Apr-2008
7
46/47
M45PE10
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
47/47

▲Up To Search▲

Price & Availability of M45PE10

	To Download M45PE10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .